1. Technical Field
A delay locked loop (DLL) is disclosed for use in a semiconductor device that employs a delay model circuit adjustable after the semiconductor circuit fabrication.
2. Description of the Related Art
Generally, a clock is used in various systems and circuitry as a reference for adjusting an operating timing and securing a much faster operation without an error. When an external clock inputted from an external circuit is employed in an internal circuit, a time delay (i.e., a clock skew) results due to the components of the internal circuit. At this time, a delay locked loop (hereinafter, referred to as a DLL) is used to compensate for such a time delay so that the internal clock can have the same phase as the external clock.
Meanwhile, since there is an advantage that the DLLs are not much affected by noises compared with a phase locked loop (PLL) that is typically used, the DLLs are widely used in synchronous semiconductor memory devices, including a double data rate synchronous DRAM (DDR SDRAM). Among them, a register controlled DLL is more generally used.
In the synchronous semiconductor memory device, basically, the register controlled DLL receives the external clock to compensate for delay components of actual clock paths and data paths, and a negative delay is fed back in advance. Through these procedures, the DLL is used to synchronize a data output with the external clock.
FIG. 1 is a block diagram of a conventional register controlled DLL in an SDRAM.
As shown, the conventional register controlled DLL uses an internal clock INT_CLK outputted from a clock input buffer 10. The clock input buffer 10 temporarily stores an external clock EXT_CLK with a voltage level of VDD to generate the internal clock INT_CLK from the external clock EXT_CLK.
The conventional register controlled DLL of the SDRAM includes a clock divider 11, a phase comparator 12, a first delay line 13, a second delay line 14, a delay controller 15, a DLL driver 16, and a delay model circuit 17.
The internal clock INT_CLK is then coupled to the clock divider 11 and the first delay line 13. At the clock divider 11, the internal clock INT_CLK is divided by 1/n (where, n is a positive integer, and in this example, n=4) and a delay monitoring clock DVD4 and an inversed delay monitoring clock DVD4Z are generated. The delay monitoring clock DVD4 is coupled to the second delay line 14 and the inversed delay monitoring clock DVD4Z is provided to the phase comparator 12. The second delay line 14 receives the delay monitoring clock DVD4 to generate a delayed delay monitoring clock which is then coupled to the delay model circuit 17. The delay model circuit 17 has a delay amount for modeling delay components of actual clock paths and data paths to thereby generate a delay model clock signal DVD4_DLY. The phase comparator 12 compares a phase of the delay model clock signal DVD4_DLY from the delay model circuit 17 with that of the inversed delay monitoring clock DVD4Z to generates a comparison signal CPR.
The delay controller 15 controls delay amount of the first and second delay lines 13 and 14 in response to the comparison signal. When the delay is locked, the DLL driver 16 drives an output from the first delay line 13 delay-locked to thereby generate a DLL clock CLK_DLL. Here, the delay controller 15 includes a shift register and a shift controller for controlling a shift direction of the shift register. The delay controller 15 repeatedly controls the delay amount until the delay locking is achieved. Meanwhile, the delay model circuit 17 is a duplicate part of the actual clock path and data path, and determines a negative delay amount of the DLL.
FIG. 2 is a timing diagram of the conventional register controlled DLL shown in FIG. 1. Hereinafter, an operation of the conventional register controlled DLL will be described with reference to FIGS. 1 and 2.
First, the clock divider 11 divides the internal clock INT_CLK by ¼ to generate the inversed delay monitoring clock DVD4Z. At this time, the inversed delay monitoring clock DVD4Z has an opposite phase to that of the delay monitoring clock DVD4.
At an initial operation, the delay monitoring clock DVD4 is passed through only one of unit delay elements contained in the second delay line 14 and is coupled to the delay model circuit 17 which delays the delay monitoring clock DVD4 by a predetermined amount and outputs the delay model signal DVD4_DLY.
Meanwhile, the phase comparator 12 compares rising edges of the inversed delay monitoring clock DVD4Z with those of the delay model clock signal DVD4_DLY to generate the comparison signal CPR. The delay controller 15 determines the delay amounts of the first and second delay lines 13 and 14 in response to the comparison signal outputted from the phase comparator 12.
Then, the delay locking is achieved when the clock has a minimal jitter by repeatedly comparing the inversed delay monitoring clock DVD4Z with the delay model clock signal DVD4_DLY, which results in the DLL driver 16 being driven to generate the DLL clock CLK_DLL synchronized with the external clock EXT_CLK.
As described above, the conventional register controlled DLL generates two divided clocks whose phases are opposite to each other. Among them, the delay monitoring clock DVD4 is delayed as much as D′ while passing through the second delay line 14 and as much as R while passing through the delay model circuit 17, so that the delay model clock signal DVD4_DLY outputted from the delay model circuit 17 is delayed as much as D′+R from the delay monitoring clock DVD4. The delay amount D′ of the second delay line 14 is repeatedly updated until the delay locking is achieved.
Here, in case where the phase is locked by adjusting D′ into D, the rising edge of the inversed delay monitoring clock DVD4Z is synchronized with that of the delay model clock signal DVD4_DLY, a following equation 1 is derived.D+R=2Ti.e.,D=2T−R  Eq.1
where T denotes a period of an external clock EXT_CLK.
Consequently, the DLL clock CLK_DLL is delayed as much as the delay amount D through the first delay line 13 and, therefore, the DLL clock CLK_DLL has the negative delay as much as the delay amount R of the delay model circuit 17 compared with the phase of the external clock EXT_CLK.
The delay amount R of the delay model circuit 17 represents a negative value of the DLL clock CLK_DLL with respect to the external clock EXT_CLK, and determines how fast the DLL clock CLK_DLL is synchronized with the external clock EXT_CLK. The substantial delay amount R of the delay model 17 is determined through a simulation in the semiconductor design before a semiconductor device fabrication. It is desired the delay amount R should be more accurately estimated in order to secure a fast delay locking operation.
FIG. 3 is a circuit diagram of the conventional delay model circuit 17.
As shown, the conventional delay model circuit 17 includes an inverter chain provided with a plurality of inverters INV1, INV2, INV3, . . . , connected in series, and a plurality of capacitor load portions 20 connected to an inverter node A1 disposed between the inverters INV1 and INV2. Each capacitor load portion 20 includes two switch 21 and 22 and an NMOS transistor 23. The switch 21 is connected between the inverter node A1 and a gate of the NMOS transistor 23 and the switch 22 is disposed between the gate and a source or a drain of the NMOS transistor 23. The NMOS transistor 23 has the source and the drain connected to each other to thereby form a capacitor.
Here, each switch 21 or 22 is constituted with a short/open switch metal, and the delay amount R of the delay model 17 is controlled by increasing or decreasing the number of the capacitors connected to the inverter node A1 and a ground. This operation can be achieved through the selective shorting or opening of the switches 21 and 22.
After completing the fabrication process of the semiconductor chip, a discrepancy between the external clock EXT_CLK and the data output timing may be measured through a test. Then, to compensate such a discrepancy, it is determined which further switches should be shorted/opened according to a test result. If so, in order to obtain such a switch configuration, newly designed masks for the semiconductor fabrication process should be prepared according to the above determination. However, there is a following problem that a new semiconductor chip may be manufactured by using the newly designed mask and, then, should be further determined through the test whether or not it is correctly operated after the fabrication. Furthermore, there may be a considerable process variation in an actual semiconductor chip in a unit of lot. As a result, there is a problem that a conventional controlling process for the delay amount of the delay model circuit 17 cannot cover or timely control such a process variation. At this time, if a semiconductor chip is fabricated completely, there always occurs the case that an operation of the chip may not accurately or quickly synchronized with the external clock EXT_CLK.
Meanwhile, in addition to the register controlled DLL, the delay model circuit is used in other kinds of DLLs, such as a digital DLL, so that the above problems are not limited to only the register controlled DLL.